Datatypes
There are 4 basic values in Verilog:
Value Level |
Description |
---|---|
0 |
Logical Zero, False |
1 |
Logical One, True |
X |
Unknown Value |
Z |
High impedance state |
The main intention of using a datatype in Verilog is to represent data storage elements like bits in a flip flop and transmission elements like wires that connect between logic gates, sequential and combinational circuits. There are mainly 2 types of data types in Verilog. They are
1. Nets
2. Regs
Nets
Nets are continuously driven by the combinational logic circuits. It means it cannot store any values. It is represented by the keyword “wire” on the lhs. Default value of a net is ‘Z’ , which is a high impedance state.
wire a, b, y;
assign y = a & b;
Here the variables are declared by the datatype of wire and for the variable y a keyword “assign” is used to drive the value of the RHS (a & b) to y.
Regs
Point to be noted, Reg is different from hardware register. Declaring a Reg doesn’t mean declaring a flip flop or a latch but it represents a storage element unlike net. A Reg is a datatype that we can use only through procedural statements.
reg a, b, y;
always@(posedge clock)
begin
y = a & b;
end
Getting Started with Verilog
For a long time, computer programming languages like FORTRAN, Pascal, and C were used to describe computer programs and their code execution is sequential. But there isn’t any language to describe the digital circuits. This is when Hardware Description Language(HDL) came into play. HDLs are even popular for verification purposes. There are mainly two types of HDL:
- Verilog HDL
- VHDL (Very High-Speed was Integrated Circuit (VHSIC) Hardware Description Language)
Note: Verilog HDL and VHDL aren’t the same. VHDL was used before Verilog came into existence. the difference between them will be discussed in the later part.
Table of Content
- What is Verilog?
- Gate Level Modeling
- Data-Flow Modeling
- Behavioral Modeling
- Operators
- Identifiers and Keywords
- Datatypes
- Module Declaration
- Classification of Verilog
- Verilog HDL Vs VHDL