Instruction-Level Parallelism
Q.1: List some techniques to enhance Instruction-Level Parallelism?
Answer:
Some of the techniques include:
- Reordering
- Out-of-Order Execution
- Speculative Execution
- Branch Prediction
Q.2: State basic difference between ILP and Pipelining Process?
Answer:
Pipeline processing has the work of breaking down instruction execution into stages, where as ILP focuses on executing the multiple instructions at the same time.
Instruction Level Parallelism
Instruction Level Parallelism (ILP) is used to refer to the architecture in which multiple operations can be performed parallelly in a particular process, with its own set of resources – address space, registers, identifiers, state, and program counters. It refers to the compiler design techniques and processors designed to execute operations, like memory load and store, integer addition, and float multiplication, in parallel to improve the performance of the processors.
Examples of architectures that exploit ILP are VLIWs and superscalar Architecture. ILP processors have the same execution hardware as RISC processors. The machines without ILP have complex hardware which is hard to implement. A typical ILP allows multiple-cycle operations to be pipelined.
Example: Suppose, 4 operations can be carried out in a single clock cycle. So there will be 4 functional units, each attached to one of the operations, branch unit, and common register file in the ILP execution hardware. The sub-operations that can be performed by the functional units are Integer ALU, Integer Multiplication, Floating Point Operations, Load, and Store. Let the respective latencies be 1, 2, 3, 2, 1.
Let the sequence of instructions by
- y1 = x1*1010
- y2 = x2*1100
- z1 = y1+0010
- z2 = y2+0101
- t1 = t1+1
- p = q*1000
- clr = clr+0010
- r = r+0001