Identifiers and Keywords
Identifier is the name given to a function, task or for a module in Verilog. These Identifiers must be in lowercase and they are case sensitive. Characters like Numbers, underscore, special characters like $ can be used for naming the identifier but they cannot be used as the first character of the identifier because they are reserved for some inbuilt function in Verilog.
For example identifier names like: my_identifier, my_identifier1, my_identifier$ can be used.
But identifiers like 1my_identifier, $my_identifier are illegal.
Getting Started with Verilog
For a long time, computer programming languages like FORTRAN, Pascal, and C were used to describe computer programs and their code execution is sequential. But there isn’t any language to describe the digital circuits. This is when Hardware Description Language(HDL) came into play. HDLs are even popular for verification purposes. There are mainly two types of HDL:
- Verilog HDL
- VHDL (Very High-Speed was Integrated Circuit (VHSIC) Hardware Description Language)
Note: Verilog HDL and VHDL aren’t the same. VHDL was used before Verilog came into existence. the difference between them will be discussed in the later part.
Table of Content
- What is Verilog?
- Gate Level Modeling
- Data-Flow Modeling
- Behavioral Modeling
- Operators
- Identifiers and Keywords
- Datatypes
- Module Declaration
- Classification of Verilog
- Verilog HDL Vs VHDL